The clock technology offers ultra-low jitter for telecom, data centre, and industrial applications, ensuring high-speed precision.
Renesas Electronics Corporation has broadened its range of timing solutions with the introduction of the new FemtoClock 3, an ultra-low 25fs-rms clock solution tailored for wireline infrastructure, data centres, and industrial applications. The series includes ultra-low jitter clock generators and jitter attenuators in 8 and 12 output versions, designed to support high-performance, user-friendly, and cost-effective clock tree architectures for cutting-edge, high-speed interconnect systems. The devices are suitable for various applications, such as telecom switches and routers, data centre switches, medical imaging systems, and broadcast audio and video.
The company claims that the devices are equipped with industry-leading phase noise and jitter levels essential for 112 Gbps SerDes rates and can also support the upcoming 224 Gbps SerDes standards using typical 48 MHz to 73 MHz crystals. The devices can generate up to four frequency domains and include integrated Low Drop Out (LDO) regulators with superior Power Supply Rejection Ratio (PSRR), simplifying the board design and reducing costs.
Some of the key features of the FemtoClock 3 Family include:
- 25 fs-rms jitter for 112 Gbps and 224 Gbps SerDes.
- Up to four frequency domains from one device.
- Options for jitter attenuation, synchronisation, and clock generation: 8 or 12 outputs.
- Low power: 1.2W at 1.8V supply.
- Integrated non-volatile memory for factory customization at no cost.
- Compact sizes: 7 x 7mm 48-pin and 9 x 9mm 64-pin VFQFPN.
- Complies with ITU-T G.8262 and G.8262.1 for synchronous Ethernet.
- Multiple modes in a single chip simplify clock configuration.
“Renesas leads the industry with best-in-class timing solutions built from decades of experience and patented technology,” said Zaher Baidas, Vice President of the Timing Division for Renesas. “FemtoClock 3 devices extend that leadership by providing multiple clock and synchronisation functions in a single device with ultra-low jitter, simplifying printed circuit board design and reducing solution area and cost.”
For more information, click here.
