By using embedded metalenses to project holograms, the method achieves precision down to fractions of a nanometer—paving the way for cost-effective 3D chip production and opening new possibilities for compact sensors and startup innovations.
Traditionally, semiconductor chips are built in two dimensions, limiting further technological advancement. To push beyond this boundary, manufacturers are turning to 3D integration, where multiple 2D chips are stacked. This requires aligning the layers with nanometer-level precision across three axes (x, y, and z). However, existing alignment methods using microscopes fall short, as the gap between chip layers—measured in hundreds of microns—prevents both layers from being viewed in focus simultaneously. Refocusing between layers risks further misalignment, according to Amir Arbabi, associate professor of electrical and computer engineering at UMass Amherst, and senior author of the study.
The new approach replaces microscopes with laser-based alignment using concentric metalenses embedded directly onto the chips. When laser light passes through these lenses, it generates overlapping holograms from the two chips. If the holograms align, the chips are precisely positioned; if not, the hologram reveals both the direction and magnitude of the misalignment. While the team aimed for 100-nanometer precision, their method achieved precision of 0.017 nm on the x and y axes and 0.134 nm on the z-axis—accurate enough to detect shifts at the atomic level. “By analyzing the light that passes through both chips, we can determine if one has moved by the size of an atom,” Arbabi explained.
Beyond chip manufacturing, this technology could power advanced displacement sensors. “You only need a laser and a camera to measure movement, heat, vibration, or acceleration,” noted Maryam Ghahremani, the study’s lead author. The method’s ability to lower production costs could benefit startups working with semiconductors, boosting innovation in the field. Arbabi emphasized that this alignment solution tackles one of the biggest challenges for semiconductor manufacturers, making advanced chip designs more accessible across the industry.
